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Translation of "ve1" in German

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The moment nominal value (MSW) is then converted into a first capacity-determining signal (ve1) by means of a characteristic diagram (8), taking into account another variable.
Then the torque setpoint (MSW) is converted into a first power-determining signal (ve1) converted.
Control system according to Claim 26, characterized in that the characteristic diagram signal (ve1(KF)) is calculated as a function of the engine speed (nMOT) and further input variables (E), in particular charge air pressure (pLL).
Control system according to Claim 26, characterized in that the map signal (ve1(KF)) as a function of the engine speed (nMOT)) and other input variables (E), in particular charge air pressure (pLL), is calculated.
The first capacity-determining signal (ve1) is corrected by means of a relative efficiency (ETAr) which definitely determines a capacity-determining signal (ve) for controlling the output moment.
The first performance-determining signal (ve1) is corrected via a relative efficiency (ETAr), which largely determines a power-determining signal (ve) for controlling the output torque.
Control system according to Claim 1, characterized in that the first signal (ve1) is determined from an engine speed (nMOT), a rotational speed difference (dnMOT) and the second signal (ve2) by means of a first controller (14).
Control system according to Claim 1, characterized in that the first signal (ve1) is determined from an engine speed (nMOT), a speed difference (dnMOT) and the second signal (ve2) by means of a first controller (14).
Winding device according to one of the preceding claims, characterized in that the elongated product being processed (VP) is a cable core of electrical and / or optical transmission elements (VE1 to VE4).
Winding device according to one of the preceding claims, characterized in that the elongated processing product (VP) is a cable core of electrical and / or optical transmission elements (VE1 with VE4).
Method according to Claim 10, in which the first and second means (VE1, VE2) are activated by actuating the respective switching elements (TPp1, TPp2; TNp1, TNp2).
The method of claim 10, wherein the activation of the first and second means (VE1, VE2) by activating the respective switching elements (TPp1, TPp2; TNpl, TNp2).
This results in an output carry (CYO) which does not take into consideration the k bit positions of the abbreviated operands (VE1 and VE2).
This results in the k bit positions of the shortened operands (VE1 and VE2) output carry not taken into account (CYO).
Process according to Claim 12, characterized in that interconnects (LB1; LB2; LB3) having a width (B1; B2; B3) of at most 75 µm are produced in the interconnect planes (VE1; VE2; VE3).
Method according to Claim 18, characterized in that in the wiring levels (VE1; VE2; VE3) conductor tracks (LB1; LB2; LB3) with a width (B1; B2; B3) of a maximum of 50 μm are generated.
Apparatus according to one of the preceding claims, characterized in that an insertion device (ELV) for inserting the stranding elements (VE1 to VE4) into the chambers (KA1 to KA4) of the accumulator (KS1) is provided.
Device according to one of the preceding claims, characterized in that an insertion device (ELV) for inserting the stranding elements (VE1 to VE4) in the chambers (KA1 to KA4) of the storage body (KS1) is provided.
In this case, this power supply system (EV) has three supply levels (VE1, VE2, VE3).
This energy supply network (EV) has three supply levels (VE1, VE2, VE3).
This allows efficient and safe operation and local control of a power supply system (EV) to which locally produced power is supplied, for example on different supply levels (VE1, VE2, VE3).
This enables more efficient and safe operation such as decentralized control of an energy supply network (EV) in which, for example, on different supply levels (VE1, VE2, VE3) decentrally generated energy is fed in.
Ve1, Ve2 are the elution volumes of the two polystyrene standards at the peak maximum
Ve1, Ve2 is the elution volume of the two polystyrene standards at the peak maximum,
A non skid chain as defined in any one of claims 1 to 8, characterized in that each of said locking elements (VE1, VE2) is manufactured as a single unit.
Anti-skid chain according to one of Claims 1 to 8, characterized in that each of the locking parts (VE1, VE2) is made in one piece.
A semiconductor memory device according to claim 4, characterized in that a plurality of emitter electrode lines (VE1 - VEN) intersecting said bit lines (BL1 -BLM) are selected in the refresh operation to simultaneously effect the refresh operation.
Semiconductor memory device according to Claim 4, characterized in that a plurality of emitter electrode lines (VE1 - VEN) which cross the bit lines (BL1 -BLM) are selected in the refresh operation in order to jointly effect the refresh operation.
Each of the three supply levels (VE1, VE2, VE3) is considered an independent control unit (RE1, RE2, RE3) that can be connected or disconnected by means of interfaces between the control units (RE1, RE2, RE3) as needed.
Each of the three levels of care (VE1, VE2, VE3) is regarded as an independent control unit (RE1, RE2, RE3), which can be connected or disconnected via interfaces between the respective control units (RE1, RE2, RE3) as required.
Method according to one of the preceding claims, characterized in that a limit-value curve (DBR) of the maximum permissible first signal (ve1) is adapted when the fault mode is set (FM = 1).
Method according to one of the preceding claims, characterized in that when the failure mode (FM = 1) is set, a limit value curve (DBR) of the maximum permissible first signal (ve1) is adapted.
In addition, the method according to the invention advantageously maintains a low number of data items to be interchanged between the supply levels (VE1, VE2, VE3).
Furthermore, the method according to the invention advantageously provides a number of data to be exchanged between the supply levels (VE1, VE2, VE3) kept low.
In order to build wiring levels (VE1, VE2, VE3) on electrically insulated supports, the conductor lattices are obtained by laser-based structuring of metallizations, and the blind holes needed for hole metallization are also laser-made.
When forming wiring layers (VE1, VE2, VE3) on electrically insulating substrates, the conductor patterns are produced by laser structuring of metallizations and the blind holes required for through-plating are also produced by means of laser radiation.
Several air-space paper-insulated cores (H1 to Hn) are assembled according to their length in a composite element (VE1 to VE5), wherein the ends can be cut to the required length if necessary.
Several loose tubes (H1 to Hn) are converted lengthwise to form a composite element (VE1 up to VE5), whereby the ends can be separated individually to the required length as required.
A semiconductor memory device according to claim 4, characterized in that said word lines (WL1 - WLN) are formed of first-layered polysilicon electrode lines and said emitter electrode lines (VE1 - VEN) are formed from second-layered polysilicon electrodes (36).
Semiconductor memory device according to Claim 4, characterized in that the word lines (WL1 - WLN) consist of a layer applied first with polysilicon electrode lines and the emitter electrode lines (VE1 - VEN) are formed from a layer applied as a second layer with polysilicon electrodes (36).
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