Is circuit and gate circuit different

DE10354501A1 - Logic circuit arrangement - Google Patents

Logic circuit arrangement Download PDF

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Publication number
DE10354501A1
DE10354501A1DE2003154501DE10354501ADE10354501A1DE 10354501 A1DE10354501 A1DE 10354501A1DE 2003154501 DE2003154501 DE 2003154501DE 10354501 ADE10354501 ADE 10354501ADE A1 10354501 A1DE 10354501ADE A110354501 A1DE
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logic
circuit arrangement
transistor
signal
mos
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DE2003154501
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DE10354501B4 (de
Inventor
Jörg GLIESE
Michael Scheppler
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Infineon Technologies AG
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Infineon Technologies AG
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Classifications

    • H-ELECTRICITY
    • H03 — BASIC ELECTRONIC CIRCUITRY
    • H03K — PULSE TECHNIQUE
    • H03K19 / 00 — Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19 / 02-Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19 / 173-Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19 / 1733 — Controllable logic circuits
    • H03K19 / 1737 — Controllable logic circuits using multiplexers

Abstract

Description

  • The invention relates to a logic circuit arrangement.
  • With the advent of digital technology and the rapid development of microprocessor technology, there was a need for programmable logic. PLDs ("Programmable Logical Devices") are integrated circuits whose logic function is defined by the user through programming. A PLD is a regularly structured architecture for digital logic operations with a large number of switches that enable a large number of signal paths. The application-specific logic function assigned to a PLD is determined by the configuration of the PLD.
  • Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.
  • a logic circuit arrangement according to its first embodiment of the invention,
  • a table in which an assignment between logic function signals and assigned logic functions according to an embodiment of the invention with two data signals are shown,
  • a logic circuit arrangement according to a second embodiment of the invention,
  • a logic circuit arrangement according to a third embodiment of the invention,
  • a schematic layout arrangement of conductor tracks according to an interconnection of the transistors of the logic circuit arrangement according to the invention according to an embodiment of the invention,
  • a logic circuit arrangement according to a fourth embodiment of the invention,
  • a logic circuit arrangement according to a fifth embodiment of the invention.
  • Identical or similar components in different figures are provided with the same reference numbers.
  • The representations in the figures are schematic and not to scale.
  • A description is given below with reference to a logic circuit arrangement in accordance with a first exemplary embodiment of the invention.
  • The logic circuit arrangement has a first data signal input and a second data signal input, at which two data signals a0 or a1 are provided. The logic circuit arrangement contains a first signal path unit which is coupled to the data signal inputs and has a plurality of n-MOS transistors (n-conduction type), the n-MOS transistors being connected to one another in such a way that they have a first Logic function of a plurality of logic functions for the logic combination of the two data signals a0, a1 realize, so that an output signal representing the result of the first logic function is provided at the output. The logic circuit arrangement also contains a second signal path unit, coupled to the data signal inputs, with a plurality of p-MOS transistors (of the p-conductivity type, which is complementary to the n-conductivity type). The p-MOS transistors are connected to one another in such a way that they have a second logic function of a plurality of different logic functions for the logic combination of the two data signals a0, a1 realize, so that an output signal representing the result of the second logic function is provided at the output, the result of the second logic function being inverse to the result of the first logic function. A further processing unit is connected between the output and a global output, by means of which output signals can be further processed in order to provide a further processed output signal y at the global output. At the global signal output of the logic circuit arrangement, the output signal y is provided, which the logic combination of the input signals a0, a1 represents according to the selected logic and has already been subjected to further processing.
  • As also shown in FIG. 4, the signal path units have a first logic function signal c at each control input0 and a second logic function signal c1 provided. By specifying these logic function signals c0, c1 the transistors or 106 of the signal path unit or are controlled in such a way that the signals a0, a1 are linked to one another by the signal path units or 105 in accordance with the first logic function or the second logic function. Thus, by specifying the logical values ​​of the logic function signals c0, c1 a very specific logic function selected.
  • The logic function signals ci, the data signals ai and the output signal y can each assume either a logic value "1" or a logic value "0".
  • The theoretical basis on which the solution according to the invention is based, which is based on Boolean logic, is described below.
  • A Boolean function can be expressed in the canonical-conjunctive normal form as an OR operation of the product terms of its n inputs (in, for example, n = 2, since two input signals a1, a0 are provided). These n inputs are 2n Assigned to product terms.
  • Applied to standard CMOS logic, the product terms for the logic value “1” of a function are implemented as a series path of p-channel transistors (in, for example: p-channel transistors). The logic value "0" is implemented accordingly as a series path made up of n-channel transistors (in: n-MOS transistors). Correspondingly, each logic function according to which signals provided at n inputs are logically linked to one another can be shown in FIGn Product terms are put together by clearly switching product terms on or off.
  • For two entrances a0 and a1 (as in) applies:
  • Every function y = f (a0, a1) is formed by adding four values ​​of the switching coefficients or logic function variables k0 to k7 to a value of logic "1" and the rest to a value of logic "0". Since in CMOS logic the p-channel transistors open with an electrical potential "0" at the control or gate connection, whereas the n-channel transistors open at an electrical potential with a value "1", the product terms can be expressed in Arrange equations (16), (17) into mutually exclusive pairs. In equations (16), (17) the first product terms are mutually exclusive, the second, the third and the fourth.
  • For the switching coefficient ki the relationship applies:
  • From equations (16), (17), (19), after combining them into four independent switching variables, c results0, c1, c2, c3:
    With
  • Equation (20) clearly corresponds to the path of p-MOS transistors in, whereas equation (21) corresponds to the path of n-MOS transistors in.
  • The logic function for forming output signal y is configured as shown in table 200 of FIG. Table 200 shows by which coefficients ci which associated logic function y can be set or is preset.
  • The solution according to the invention is characterized by an increased interference immunity of the circuit and by a very compact feasibility (layout of the logic cell). The solution is also very scalable in terms of the number of inputs and outputs.
  • In certain application scenarios, the universal logic cell exhibits a reduced switching delay with a reduced energy consumption under comparable boundary conditions compared to competing solutions.
  • The invention can be used in the context of FPGA technology or as a combinatorial core cell of a structured ASIC. In addition, the invention can be used particularly advantageously wherever the implementation of a subset of logic functions is more complex than the use of a universal logic cell.
  • A description is given below with reference to a semiconductor technology implementation of the function according to equations (20), (21) based on transistors.
  • In the logic circuit arrangement from FIG. 1, a first data signal a is at a first data signal input0 provided. Furthermore, a second data signal a1 provided. By means of a first inverter circuit, the first data signal a0 the complementary signal
    educated. The first data signal input is coupled to the gate region of a first n-MOS inverter transistor. Furthermore, the first data signal input is coupled to the gate connection of a first p-MOS inverter transistor. A first source / drain region of the first p-MOS inverter transistor is brought to the electrical supply potential. The second source / drain region of the first p-MOS inverter transistor is coupled to a first source / drain region of the first n-MOS inverter transistor, the second source / drain region of which is connected to the electrical ground potential is brought.
  • Furthermore, a second inverter circuit is provided, by means of which from the second data signal a1 its logically complementary signal
    is formed. The second data signal input is coupled to the gate terminals of a second n-MOS inverter transistor and a second p-MOS inverter transistor, which transistors form the second inverter circuit. A first source / drain region of the second p-MOS inverter transistor is coupled to the first source / drain region of the first p-MOS inverter transistor, whereas the second source / drain terminal of the second p -MOS inverter transistor is coupled to a first source / drain terminal of the second n-MOS inverter transistor. The second source / drain connection of the second n-MOS inverter transistor is brought to the electrical ground potential.
  • As shown in FIG. 4, the data signals and their logically complementary values ​​are provided to a signal path unit. The signal is at a first signal path input
    provided. The signal is at a second signal path input
    provided. The signal a is at a third signal path input0 provided. The signal a is at a fourth signal path input1 provided.
  • The signal path unit is formed from first to twelfth p-MOS logic transistors to and from first to twelfth n-MOS logic transistors to. The first to twelfth p-MOS logic transistors to form a first signal path sub-unit, whereas the first to twelfth n-MOS logic transistors to form a second signal path sub-unit.
  • A first logic function signal c is at a first logic function input0 created. A second logic function signal c is at a second logic function input1 provided. A third logic function signal c is at a third logic function input2 provided. A fourth logic function signal c is at a fourth logic function input3 provided. The logic function inputs to can also be referred to as control inputs of the logic circuit arrangement.
  • The fourth logic function input is coupled to the gate connection of the ninth p-MOS logic transistor and to the gate connection of the first n-MOS logic transistor. The third logic function input is coupled to the gate connections of the tenth p-MOS logic transistor and the second n-MOS logic transistor. The second logic function input is coupled to the gate connections of the eleventh p-MOS logic transistor and the third n-MOS logic transistor. The first logic function input is coupled to the gate connections of the twelfth p-MOS logic transistor and the fourth n-MOS logic transistor.
  • The first data signal input is connected to the gate connection of the fifth n-MOS logic transistor, the sixth p-MOS logic transistor, the seventh n-MOS logic transistor and the fourth p-MOS logic transistor coupled. The second data signal input is connected to the gate connections of the ninth n-MOS logic transistor, the tenth n-MOS logic transistor, the third p-MOS logic transistor and the eighth p-MOS logic transistor coupled. The third data signal input is connected to the gate connections of the fifth p-MOS logic transistor, the sixth n-MOS logic transistor, the seventh p-MOS logic transistor and the eighth n-MOS logic transistor coupled. The fourth data signal input is connected to the gate connections of the first p-MOS logic transistor, the second p-MOS logic transistor, the eleventh n-MOS logic transistor and the twelfth n-MOS logic transistor coupled.
  • First source / drain connections of the first to fourth p-MOS logic transistors are brought to the electrical potential of the supply voltage. The second source / drain connection of the first p-MOS logic transistor is coupled to a first source / drain connection of the fifth p-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the ninth p-MOS logic transistor is coupled. The second source / drain connection of the second p-MOS logic transistor is coupled to a first source / drain connection of the sixth p-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the tenth p-MOS logic transistor is coupled. The second source / drain connection of the third p-MOS logic transistor is coupled to a first source / drain connection of the seventh p-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the eleventh p-MOS logic transistor is coupled. The second source / drain connection of the fourth p-MOS logic transistor is coupled to a first source / drain connection of the eighth p-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the twelfth p-MOS logic transistor is coupled.
  • The second source / drain connections of the ninth to twelfth p-MOS logic transistors to are coupled to the output and to first source / drain connections of the first to fourth n-MOS logic transistors to.The second source / drain connection of the first n-MOS logic transistor is coupled to a first source / drain connection of the fifth n-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the ninth n-MOS logic transistor is coupled. The second source / drain connection of the second n-MOS logic transistor is coupled to a first source / drain connection of the sixth n-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the tenth n-MOS logic transistor is coupled. The second source / drain connection of the third n-MOS logic transistor is coupled to a first source / drain connection of the seventh n-MOS logic transistor, the second source / drain connection of which is coupled to a first source - / Drain connection of the eleventh n-MOS logic transistor is coupled. Furthermore, the second source / drain terminal of the fourth n-MOS logic transistor is coupled to a first source / drain terminal of the eighth n-MOS logic transistor, the second source / drain terminal of which is coupled to a first Source / drain connection of the twelfth n-MOS logic transistor is coupled. The second source / drain connections of the ninth to twelfth n-MOS logic transistors to are coupled to one another and brought to the electrical ground potential.
  • The output signal y is at the outputint provided.
  • From the output signal yint at the output, using a third inverter circuit, the logic inverse y0 formed, which is provided at a global output. The output signal yint is passed through the third inverter circuit, formed from a third n-MOS inverter transistor and a third p-MOS inverter transistor. The output is coupled to the gate connections of the transistors. A first source / drain connection of the third p-MOS inverter transistor is at the electrical supply potential