Why is nwell used in VLSI technology

Technology CAD - Computer Simulation of IC Processes and Devices

Chapter 1. Technology-Oriented CAD

The rapid evolution and explosive growth of integrated circuit technology have impacted society more than any other technological development of the 20th century. Integrated circuits (ICs) are used universally, in everything from computer technology, communications, and information processing to transportation, residential and recreational applications. In fact, it is becoming difficult to find applications in which IC electronics have not been used. The expanding use of IC technology requires more accurate circuit analysis methods and tools, prompting the introduction of computers into the design process. The goal of this book is to build a firm foundation in the use of Computer-Assisted techniques for IC device and process design (CAD). Both practical and analytical viewpoints are stressed to give the reader the background necessary to appreciate CAD tools and to feel comfortable with their use.
Robert W. Dutton, Zhiping Yu

Chapter 2. Introduction to SUPREM

While the exact form that VLSI technology would take in the future was uncertain in late 1970s, it seemed evident that costly and time consuming empirical approaches to developing and optimizing such technology are a luxury few will be able to afford or wish to justify. A far more attractive alternative is the formulation of accurate models of the basic physical processes involved, and their implementation in a comprehensive computer program. Such a program would allow predictions of device structures resulting from any proposed fabrication sequence and would minimize the need for empirical iterative attempts. Since its inception, the process simulator SUPREM has been one such attempt to realize this goal. Beginning with SUPREM I and proceeding to SUPREM II and III, each version has drawn from the models and physical understanding of fabrication processes then available.
Robert W. Dutton, Zhiping Yu

Chapter 3. Device CAD

Device and circuit design involve detailed understanding of device models. For both these design stages, details such as the role of substrate doping on threshold voltage and capacitances of MOSFETs must be characterized in terms of parametric equations.
Robert W. Dutton, Zhiping Yu

Chapter 4. PN Junctions

In the previous chapters we have introduced process and device simulation - both data structures and their application in modeling semiconductor devices. In the next few chapters we consider in greater depth the physical effects in semiconductor devices based on analytical formulations as well as using the SUPREM and SEDAN / PISCES tools. In Chapter 3 the basic formulation of decoupling the device equations was introduced. Tracing the literature of semiconductor device analysis one finds this approach used again and again to simplify and to separate the problem into a set of smaller problems, each with independent analytic solutions. For a large number of problems this approach has worked quite well. Most introductory textbooks in the field use this approach and undoubtedly the reader has had exposure to such material. Starting with the next few sections of this chapter there will be a brief summary of many of the key results. Although it is helpful if the reader has seen this material before, it is sufficiently self-contained that all the basic points are presented and discussed. The motivation for this review is two-fold. First, as stated above, it provides a self-contained glossary of equations and modeling concepts. Second, as simulation results are presented it will be apparent how the, “exact,” results fit into the fabric of the analytical results. More precisely, to validate the assumptions imposed in order to separate and solve the device equations, the simulation results can directly be compared.
Robert W. Dutton, Zhiping Yu

Chapter 5. MOS Structures

The previous chapter discussed the analysis of pn junctions using both analytical and numerical techniques. The pn junction is an essential component in all aspects of silicon IC’s. In bipolar technology, it forms the active source for injecting carriers and the collecting junction to extract them. In Chapter 6 we will return to the discussion of these bipolar applications. For MOS technology the pn junction is an essential, “parasitic,” component. Namely, the source and drain junctions are indeed diodes but their main purpose is to form lateral majority-carrier sources and sinks to a gate-induced inversion layer (inverted with respect to the substrate which is in the opposite carrier type from the source and drain ). In this chapter we will analyze the MOS gate structure in conjunction with our previous analysis of the pn junction in order to study the MOSFET. Specifically, we will build upon the Poisson’s solutions from Chapter 4 and introduce the additional concepts needed to understand inversion layers in the MOS device. By adding the actual source and drain regions in the form of pn junctions, we will create and analyze the MOSFET. Based on the approach used in Chapter 4, we will first develop the analytic models. Subsequently, we will use SEDAN / PISCES to explore and develop a deeper understanding of the analytic results. A range of technology dependencies can be understood and quantified where the first-principle analytic models break down.
Robert W. Dutton, Zhiping Yu

Chapter 6. Bipolar Transistors

The previous two chapters have discussed the pn junction, the MOS capacitor, and the FET device. For the pn junction, we considered minority carrier injection into material of the opposite carrier type. In the MOSFET, we create a conducting channel between source and drain regions (both of opposite carrier type to the substrate) by inverting the carrier type of the substrate (or the well). In this chapter we consider the bipolar transistor and its operation in detail. Bipolar transistor operation hinges on the proximity of two pn junctions, separated by less than a diffusion length for minority carriers. If one junction is forward biased and the other reverse biased, it is possible to inject (or “emit,”) carriers from the forward biased junction and, “collect,” these carriers at the adjacent, reverse biased junction.
Robert W. Dutton, Zhiping Yu

Chapter 7. BiCMOS Technology

The preceding three chapters have discussed the process and device effects of diodes, MOSFETs, and bipolar transistors. The underlying theme of CMOS technology was used for each of the device structures considered. In Chapter 1 we introduced several evolutionary versions of technology, including metal-gate p-well, poly-gate n-well, and twin-tub CMOS. The choice of n-well CMOS as the pedagogical example was one of convenience, owing to Stanford’s use of that technology in the early 1980s. In this chapter we consider the evolution of CMOS towards bipolar-compatible CMOS or BiCMOS technology. The possibility of developing BiCMOS is attractive because a number of performance improvements are possible. Namely, the bipolar device offers current driving, device matching, and threshold control superior to MOS. These features have led to high-speed gate arrays [7.1] and static RAMs with superior performance [7.2]. The major disadvantages of BiCMOS are increased process complexity and reduced yield due to emitter-collector shorts. In addition, the merged process can reduce performance of either the best CMOS or bipolar technology by itself. For example, by using the n-well as part of the bipolar device, the process may shift in a direction which raises the body coefficient, γ, for MOS operation (for details, see section 7.2). Conversely, constraints on epitaxial and base doping levels as imposed by the MOS devices may reduce bipolar performance - for example, lower breakdown voltage and higher output conductance (i.e. lower V.A.). In short, the simultaneous optimization of both bipolar and MOS devices, while at the same time trying to minimize the masking and process complexity, is a major research challenge.
Robert W. Dutton, Zhiping Yu